This invention relates to a method of manufacturing a vertical power transistor trench-gate semiconductor device, and to such a device made by the method.
Such a semiconductor device is known in which the device comprises a semiconductor body with trenches extending into the semiconductor body from a surface thereof and an insulating layer provided between gate material in the trenches and the semiconductor body adjacent the trenches; wherein the device has an active transistor cell area, each transistor cell having source and drain regions which are separated by a channel-accommodating body region adjacent a trench-gate, and a source electrode contacting the source regions on the semiconductor body surface and being insulated from the gate material in the trenches; and wherein the device has an inactive area without source regions, said insulating layer extending from the trenches to provide a top surface insulating layer on the semiconductor body surface in the inactive area, further gate material extending from the gate material in the trenches in the inactive area and onto the top surface insulating layer, and a gate electrode contacting the further gate material.
U.S. Pat. No. 5,795,792 (Nishihara) discloses a device having the known features which we have defined above. The background art discussion in this U.S. patent document indicates that chip size reduction and performance improvement require reduction of trench widths, but that if trench width is reduced too much it can be difficult directly to form a contact with the gate material buried in the trench. It is therefore a generally practised approach to lead out the gate material from inside the trench to the main surface of the semiconductor substrate for contact with a gate electrode on that surface. This is in accordance with the feature we have described above wherein the device comprises further gate material extending from the gate material in the trenches in the inactive area and onto the top surface insulating layer, and a gate electrode contacting the further gate material. Nishihara is concerned with insulated-gate devices where the gate insulating layer (that is the insulating layer and the top surface insulating layer we have defined above) is a silicon oxide film, and there is a discussion of the further problem that conventional processing results in a thinning of this silicon oxide film just at the upper end corner portion of the trench where the gate material is led out from the trench to the main surface and that this thinning can greatly reduce the breakdown voltage of the silicon oxide film. The inventive disclosure of Nishihara concerns methods for increasing the silicon oxide thickness at this upper end corner portion of the trench. Both the conventional process acknowledged by Nishihara and the inventive process disclosed by Nishihara involve first providing the channel-accommodating body region with this conductivity type region also extending to underneath where the gate electrode will be, then forming the trenches and the gate insulating layer, then depositing gate material and patterning this gate material in one step so that it is in the trenches and is also led out to the main surface for contact with the gate electrode.
It is an aim of the present invention to provide an alternative and advantageous method both for providing the channel-accommodating body region and for providing contact to the gate electrode.
According to the present invention there is provided a method of manufacturing a vertical power transistor trench-gate semiconductor device having the known features which we have defined above; the method including the steps of:
(a) providing the semiconductor body with a first layer extending to the semiconductor body surface in the active and inactive areas, the first layer being of a first conductivity type suitable for the drain regions;
(b) forming the trenches extending into the first layer in the active and inactive areas;
(c) while the first layer still extends to the semiconductor body surface, providing the insulating layer in the trenches in the active and inactive areas, and providing the top surface insulating layer in the inactive area;
(d) depositing a first material in the trenches and planarising the first material to the top of the trenches in the active and inactive areas;
(e) after steps (c) and (d), forming a second layer extending from the semiconductor body surface in the active and inactive areas, the second layer being of a second conductivity type, opposite to the first conductivity type, suitable for the channel-accommodating body regions in the active area;
(f) after step (e), forming the source regions in the active area; and
(g) also after step (e), providing the further gate material in the inactive area.
Forming the second layer in step (e) after providing the insulating layers in step (c) in the method of the present invention has advantages in optimising the channel profile of the device in operation, particularly in the case where these insulating layers are formed by oxidation of the semiconductor body first layer, as will be explained later in the description of embodiments of the invention.
The effect of having the second layer, which forms the channel-accommodating body regions in the active area, present in the inactive area underneath the gate electrode is to counteract the concentration of electric field at the bottom corners of the trenches in the inactive area which would otherwise occur with resulting disadvantageous reduction in breakdown voltage of the device in operation. This effect will be explained in more detail later in the description of embodiments of the invention. It seems that this effect of reducing the electric field at the bottom corners of the trenches in the inactive area would also be present in the structure disclosed in the Nishihara US patent, although this is not mentioned in this document whose inventive disclosure is concerned with breakdown voltage at the top corners of the trenches in the inactive area. For reasons which will be explained in the later description of embodiments of the invention, breakdown at the bottom corners of the trenches in the inactive area is a different problem from breakdown at the top corners of these trenches.
Thus the method of the present invention enables the second layer to be formed in the active area after forming the gate insulating layers in the trench-gate trenches so as to optimise the channel profile of the device, and enables this second layer to be formed at the same time in the inactive area so as to reduce the electric field at the bottom corners of the trenches in the inactive area.
As defined in claim 3, the first material which is deposited and planarised in step (d) may be the device gate material. In this case the device gate material and the device further gate material are provided in two separate steps, respectively (d) and (g), before and after forming the second layer in the active and inactive areas in step (e), this step (e) being after providing the insulating layer in the trenches and the top surface insulating layer in the inactive area in step (c).
Alternatively, as defined in claim 6, after step (e) and before step (g) the first material may be removed from the trenches, and in step (g) a second material may be deposited in the trenches and on the top surface insulating layer in the inactive area, the second material being patterned to provide the device gate material and the device further gate material. In this case the device gate material and the device further gate material are provided in a single step, step (g), again after forming the second layer in the active and inactive areas in step (e), this step (e) being after providing the insulating layers in step (c).
In both methods as described above, that is as defined in claim 3 and as defined in claim 6, preferably in step (c) the insulating layer in the trenches, the top surface insulating layer in the inactive area and a further top surface insulating layer in the active area are formed simultaneously, and the second layer is formed in step (e) using dopant implantation through the top surface insulating layer and through the further top surface insulating layer. In this case, the source regions may be formed in step (f) using dopant implantation through the further top surface insulating layer, the further top surface insulating layer being removed before providing the source electrode.